%0 Conference Paper %1 conf/isscc/TangGSXSH18 %A Tang, Liangxiao %A Gai, Weixin %A Shi, Linqi %A Xiang, Xiao %A Sheng, Kai %A He, Ai %B ISSCC %D 2018 %I IEEE %K dblp %P 114-116 %T A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2018.html#TangGSXSH18 %@ 978-1-5090-4940-0

@inproceedings{conf/isscc/TangGSXSH18, added-at = {2023-06-26T00:00:00.000+0200}, author = {Tang, Liangxiao and Gai, Weixin and Shi, Linqi and Xiang, Xiao and Sheng, Kai and He, Ai}, biburl = {https://www.bibsonomy.org/bibtex/2a38b1829ef5a7de9da1ad42fc0a6f20a/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2018}, ee = {https://doi.org/10.1109/ISSCC.2018.8310210}, interhash = {37f3ecda0afb220f1f1a187140dd9fe7}, intrahash = {a38b1829ef5a7de9da1ad42fc0a6f20a}, isbn = {978-1-5090-4940-0}, keywords = {dblp}, pages = {114-116}, publisher = {IEEE}, timestamp = {2024-04-10T11:03:54.000+0200}, title = {A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2018.html#TangGSXSH18}, year = 2018 }