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23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.
T. Ting, G. Wang, M. Wang, C. Wu, C. Wang, C. Lo, L. Tien, D. Yuan, Y. Hsieh, J. Lai, W. Hsu, C. Huang, C. Chen, Y. Chou, D. Kwai, Z. Wang, W. Wu, S. Tomishima, P. Stolt, und S. Lu.ISSCC, Seite 404-405. IEEE, (2017)
Metadaten
- BibTeX-Schlüssel
- conf/isscc/TingWWWWLTYHLHH17
- Eintragstyp
- inproceedings
- Buchtitel
- ISSCC
- Jahr
- 2017
- Seiten
- 404-405
- Verlag
- IEEE
- BibTeX-Querverweis
- conf/isscc/2017
- ee
- https://doi.org/10.1109/ISSCC.2017.7870432
- isbn
- 978-1-5090-3758-2
- URL
- http://dblp.uni-trier.de/db/conf/isscc/isscc2017.html#TingWWWWLTYHLHH17
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%1 conf/isscc/TingWWWWLTYHLHH17
%A Ting, Tah-Kang Joseph
%A Wang, Gyh-Bin
%A Wang, Ming-Hung
%A Wu, Chun-Peng
%A Wang, Chun-Kai
%A Lo, Chun-Wei
%A Tien, Li-Chin
%A Yuan, Der-Min
%A Hsieh, Yung-Ching
%A Lai, Jenn-Shiang
%A Hsu, Wen-Pin
%A Huang, Chien-Chih
%A Chen, Chi-Kang
%A Chou, Yung-Fa
%A Kwai, Ding-Ming
%A Wang, Zhe
%A Wu, Wei
%A Tomishima, Shigeki
%A Stolt, Patrick
%A Lu, Shih-Lien
%B ISSCC
%D 2017
%I IEEE
%K dblp
%P 404-405
%T 23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2017.html#TingWWWWLTYHLHH17
%@ 978-1-5090-3758-2
@inproceedings{conf/isscc/TingWWWWLTYHLHH17,
added-at = {2021-10-14T00:00:00.000+0200},
author = {Ting, Tah-Kang Joseph and Wang, Gyh-Bin and Wang, Ming-Hung and Wu, Chun-Peng and Wang, Chun-Kai and Lo, Chun-Wei and Tien, Li-Chin and Yuan, Der-Min and Hsieh, Yung-Ching and Lai, Jenn-Shiang and Hsu, Wen-Pin and Huang, Chien-Chih and Chen, Chi-Kang and Chou, Yung-Fa and Kwai, Ding-Ming and Wang, Zhe and Wu, Wei and Tomishima, Shigeki and Stolt, Patrick and Lu, Shih-Lien},
biburl = {https://www.bibsonomy.org/bibtex/2f3fc18ff7d2bd82ea39653623af47536/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2017},
ee = {https://doi.org/10.1109/ISSCC.2017.7870432},
interhash = {b188f11db95e58cf5f97d6231cc35a20},
intrahash = {f3fc18ff7d2bd82ea39653623af47536},
isbn = {978-1-5090-3758-2},
keywords = {dblp},
pages = {404-405},
publisher = {IEEE},
timestamp = {2024-04-10T11:03:47.000+0200},
title = {23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2017.html#TingWWWWLTYHLHH17},
year = 2017
}