%0 Conference Paper %1 conf/iscas/LimaPRRMCCSB19 %A Lima, Vitor G. %A Paim, Guilherme %A Rocha, Leandro M. G. %A da Rosa Jr., Leomar S. %A Marques, Felipe S. %A da Costa, Eduardo A. C. %A Camargo, Vinicius V. %A Soares, Rafael %A Bampi, Sergio %B ISCAS %D 2019 %I IEEE %K dblp %P 1-5 %T Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2019.html#LimaPRRMCCSB19 %@ 978-1-7281-0397-6

@inproceedings{conf/iscas/LimaPRRMCCSB19, added-at = {2022-04-09T00:00:00.000+0200}, author = {Lima, Vitor G. and Paim, Guilherme and Rocha, Leandro M. G. and da Rosa Jr., Leomar S. and Marques, Felipe S. and da Costa, Eduardo A. C. and Camargo, Vinicius V. and Soares, Rafael and Bampi, Sergio}, biburl = {https://www.bibsonomy.org/bibtex/27891e7195e2356229251cebacf22ac4d/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2019}, ee = {https://doi.org/10.1109/ISCAS.2019.8702687}, interhash = {e732019a562bf8ae4ad8223528d3ddd7}, intrahash = {7891e7195e2356229251cebacf22ac4d}, isbn = {978-1-7281-0397-6}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2024-04-10T17:48:30.000+0200}, title = {Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2019.html#LimaPRRMCCSB19}, year = 2019 }