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Disambiguation of "Camargo, Vinicius V."

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Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.

, , , , , , , , and . ISCAS, page 1-5. IEEE, (2019)

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Vinícius Liebel

Vinícius Maran

Vinicius Malatesta

Héctor Camargo

Alfonso Camargo

 

Other publications of authors with the same name

Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions., , , and . ISCAS, page 1744-1748. IEEE, (2022)Evaluating the Impact of BTI on Hiding Countermeasures for DPA and DEMA Attacks., , , and . ISCAS, page 1-5. IEEE, (2021)A Novel Sizing Method Aiming Security Against Differential Power Analysis., , , , , and . ICECS, page 429-432. IEEE, (2018)Transistor Reordering for Electrical Improvement in CMOS Complex Gates., , , and . SBCCI, page 1-6. IEEE, (2022)Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies., , , , and . ISCAS, page 1-5. IEEE, (2020)Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing., , , , , , , , and . ISCAS, page 1-5. IEEE, (2019)Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design., , , , and . LASCAS, page 1-4. IEEE, (2022)Fast Chaotic Image Encryption with Simultaneous Permutation and Diffusion for IoT Applications., , , , and . GLOBECOM, page 5481-5486. IEEE, (2022)Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (2): 280-285 (2014)NBTI-aware technique for transistor sizing of high-performance CMOS gates., , , , and . LATW, page 1-5. IEEE, (2009)