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Disambiguation of "Paim, Guilherme"

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Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.

, , , , , , , , and . ISCAS, page 1-5. IEEE, (2019)

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Guilherme Lepski

A comparative analysis of human adult mesenchymal and fetal neuronal stem cells with regard to their neurogenic potential. Uni Freiburg, (2009)

Rebecca Paimann

Wilhelmus Johannes Paimans

Rebecca Paimann

Volker Paimann

 

Other publications of authors with the same name

Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design., , , , and . ICECS, page 1-4. IEEE, (2020)Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination., , , , , and . ICECS, page 1-4. IEEE, (2020)Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform., , , , and . NEWCAS, page 25-28. IEEE, (2017)Exploiting absolute arithmetic for power-efficient sum of absolute differences., , , , , , and . ICECS, page 522-525. IEEE, (2017)Power efficient 2-D rounded cosine transform with adder compressors for image compression., , , and . ICECS, page 348-351. IEEE, (2015)Physical implementation of an ASIC-oriented SRAM-based viterbi decoder., , , , , , and . ICECS, page 526-529. IEEE, (2017)A Fixed-Point Natural Logarithm Approximation Hardware Design Using Taylor Series., , , and . NGCAS, page 53-56. IEEE, (2018)An efficient sub-sample interpolator hardware for VP9-10 standards., , , , , , , and . ICIP, page 2167-2171. IEEE, (2016)Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture., , , , , , , and . MWSCAS, page 1084-1087. IEEE, (2020)AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation., , , , and . DSN-W, page 183-186. IEEE, (2023)