%0 Conference Paper %1 conf/vlsit/SuzukiYYGOKAKCM23 %A Suzuki, Junnosuke %A Yu, Jaehoon %A Yasunaga, Mari %A García-Arias, Ángel López %A Okoshi, Yasuyuki %A Kumazawa, Shungo %A Ando, Kota %A Kawamura, Kazushi %A Chu, Thiem Van %A Motomura, Masato %B VLSI Technology and Circuits %D 2023 %I IEEE %K dblp %P 1-2 %T Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#SuzukiYYGOKAKCM23 %@ 978-4-86348-806-9

@inproceedings{conf/vlsit/SuzukiYYGOKAKCM23, added-at = {2024-02-05T00:00:00.000+0100}, author = {Suzuki, Junnosuke and Yu, Jaehoon and Yasunaga, Mari and García-Arias, Ángel López and Okoshi, Yasuyuki and Kumazawa, Shungo and Ando, Kota and Kawamura, Kazushi and Chu, Thiem Van and Motomura, Masato}, biburl = {https://www.bibsonomy.org/bibtex/2d3f584a5ee0fda8195a78485f286bf74/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2023}, ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185293}, interhash = {67c6d62825e96a082f9ed6642a950d6b}, intrahash = {d3f584a5ee0fda8195a78485f286bf74}, isbn = {978-4-86348-806-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:01.000+0200}, title = {Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#SuzukiYYGOKAKCM23}, year = 2023 }