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Disambiguation of "Ando, Kota"

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Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.

, , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Ramachandra Kota

Lalitha Kota

Kota Miura

Kota Murali

Junko Ando

 

Other publications of authors with the same name

APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control., , , , , , and . IPDPS Workshops, page 414-420. IEEE, (2022)Multicoated Supermasks Enhance Hidden Networks., , , , , , , and . ICML, volume 162 of Proceedings of Machine Learning Research, page 17045-17055. PMLR, (2022)Exploring optimized accelerator design for binarized convolutional neural networks., , , , , and . IJCNN, page 2510-2516. IEEE, (2017)Out-of-distribution Data Detection using Bayesian Convolutional Neural Network with Variational Inference., , , , and . IJCNN, page 1-8. IEEE, (2024)A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems., , , , , , and . IEICE Trans. Inf. Syst., 106 (12): 1969-1978 (December 2023)ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation., , , , , , and . CANDAR, page 215-220. IEEE, (2020)Accelerating deep learning by binarized hardware., , , , , , , and . APSIPA, page 1045-1051. IEEE, (2017)QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS., , , , , , , , and . ISSCC, page 216-218. IEEE, (2018)Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner., , , , , , and . HCS, page 1-21. IEEE, (2021)Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet., , , , , , , , and . ISSCC, page 1-3. IEEE, (2022)