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Disambiguation of "Kawamura, Kazushi"

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Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.

, , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Hiroki Kawamura

Hiroshi Kawamura

Katsutoshi Kawamura

Eisuke Kawamura

Eiko Kawamura

 

Other publications of authors with the same name

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension., , , , , , , , , and 2 other author(s). ISSCC, page 42-43. IEEE, (2023)FPGA-based Heterogeneous Solver for Three-Dimensional Routing., , , , , and . ASP-DAC, page 11-12. IEEE, (2020)A partial redundant fault-secure high-level synthesis algorithm for RDR architectures., , , and . ISCAS, page 1736-1739. IEEE, (2013)Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA., , , , and . ICCE, page 1-2. IEEE, (2024)Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA., , , , , and . ICCE, page 1-2. IEEE, (2024)A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs., , , , and . APCCAS, page 244-247. IEEE, (2014)A high-performance circuit design algorithm using data dependent approximation., , and . ISOCC, page 95-96. IEEE, (2016)Rotator-based multiplexer network synthesis for field-data extractors., , , , and . SoCC, page 194-199. IEEE, (2016)A loop structure optimization targeting high-level synthesis of fast number theoretic transform., , and . ISQED, page 106-111. IEEE, (2018)