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A new balanced 4-moduli set 2k, 2n - 1, 2n + 1, 2n+1-1 and its reverse converter design for efficient fir filter implementation.

G. Chalivendra, V. Hanumaiah, and S. Vrudhula. ACM Great Lakes Symposium on VLSI, page 139-144. ACM, (2011)

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Gayathri Nadarajan

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A new balanced 4-moduli set 2k, 2n - 1, 2n + 1, 2n+1-1 and its reverse converter design for efficient fir filter implementation.G. Chalivendra, V. Hanumaiah, and S. Vrudhula. ACM Great Lakes Symposium on VLSI, page 139-144. ACM, (2011)A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS.S. Leshner, K. Berezowski, X. Yao, G. Chalivendra, S. Patel, and S. Vrudhula. ISVLSI, page 210-215. IEEE Computer Society, (2010)

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Disambiguation of "Chalivendra, Gayathri"

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A new balanced 4-moduli set 2k, 2n - 1, 2n + 1, 2n+1-1 and its reverse converter design for efficient fir filter implementation.

Please choose a person to relate this publication to

Gayathri Nadarajan

Other publications of authors with the same name

Disambiguation

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Disambiguation of "Chalivendra, Gayathri"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A new balanced 4-moduli set 2k, 2n - 1, 2n + 1, 2n+1-1 and its reverse converter design for efficient fir filter implementation.

Please choose a person to relate this publication to

Gayathri Nadarajan

Other publications of authors with the same name

Disambiguation

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A new balanced 4-moduli set 2k, 2n - 1, 2n + 1, 2n+1-1 and its reverse converter design for efficient fir filter implementation.