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A new balanced 4-moduli set 2k, 2n - 1, 2n + 1, 2n+1-1 and its reverse converter design for efficient fir filter implementation.

G. Chalivendra, V. Hanumaiah, and S. Vrudhula. ACM Great Lakes Symposium on VLSI, page 139-144. ACM, (2011)

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Sarma Siahaan

Hassan Rahim B K

Gerhard K B Alberti

Nima Sarmadi

Srikrishna Sarma

Other publications of authors with the same name

Fast and robust differential flipflops and their extension to multi-input threshold gates.J. Yang, N. Kulkarni, J. Davis, and S. Vrudhula. ISCAS, page 822-825. IEEE, (2015)Statistical waveform and current source based standard cell models for accurate timing analysis.A. Goel, and S. Vrudhula. DAC, page 227-230. ACM, (2008)Throughput optimal task allocation under thermal constraints for multi-core processors.V. Hanumaiah, R. Rao, S. Vrudhula, and K. Chatha. DAC, page 776-781. ACM, (2009)Statistical library characterization using arbitrary polynomial chaos.M. Ince, S. Ozev, and S. Vrudhula. LASCAS, page 1-4. IEEE, (2017)A fast, energy efficient, field programmable threshold-logic array.N. Kulkarni, J. Yang, and S. Vrudhula. FPT, page 300-305. IEEE, (2014)Combinational equivalence checking for threshold logic circuits.T. Gowda, S. Vrudhula, and G. Konjevod. ACM Great Lakes Symposium on VLSI, page 102-107. ACM, (2007)Power Reduction of Functional Units Considering Temperature and Process Variations.D. Kannan, A. Shrivastava, S. Bhardwaj, and S. Vrudhula. VLSI Design, page 533-539. IEEE Computer Society, (2008)Temperature and Process Variations Aware Power Gating of Functional Units.D. Kannan, A. Shrivastava, V. Mohan, S. Bhardwaj, and S. Vrudhula. VLSI Design, page 515-520. IEEE Computer Society, (2008)Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.P. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J. sun Seo, Y. Cao, and S. Yu. DATE, page 854-859. ACM, (2015)Statistical Timing Analysis Using Bounds.A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula. DATE, page 10062-10067. IEEE Computer Society, (2003)

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Disambiguation of "Vrudhula, Sarma B. K."

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A new balanced 4-moduli set 2k, 2n - 1, 2n + 1, 2n+1-1 and its reverse converter design for efficient fir filter implementation.

Please choose a person to relate this publication to

Sarma Siahaan

Hassan Rahim B K

Gerhard K B Alberti

Nima Sarmadi

Srikrishna Sarma

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Vrudhula, Sarma B. K."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A new balanced 4-moduli set 2k, 2n - 1, 2n + 1, 2n+1-1 and its reverse converter design for efficient fir filter implementation.

Please choose a person to relate this publication to

Sarma Siahaan

Hassan Rahim B K

Gerhard K B Alberti

Nima Sarmadi

Srikrishna Sarma

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A new balanced 4-moduli set 2k, 2n - 1, 2n + 1, 2n+1-1 and its reverse converter design for efficient fir filter implementation.