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pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.

I. Choi, S. Hong, K. Kim, J. Hwang, S. Woo, Y. Kim, C. Cho, E. Lee, H. Lee, M. Jung, H. Jung, J. Hwang, J. Yoon, W. Lim, H. Yoo, W. Lee, J. Oh, D. Lee, J. Lee, J. Kim, Y. Kim, S. Park, B. Ho, B. Na, H. Choi, C. Lee, S. Lee, H. Shin, Y. Lee, J. Ryu, S. Shin, S. Park, D. Lim, S. Bae, Y. Sohn, T. Oh, and S. Hwang. ISSCC, page 234-236. IEEE, (2024)

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Jae-Hun Kim

Jae-Hun Jeoung

Kang-Hun Lee

Hun Dae Lee

Seung-Hun Lee

Other publications of authors with the same name

Fast half-pixel motion estimation based on a directional search and a linear model.Y. Lee, J. Lee, and J. Ra. VCIP, volume 5150 of Proceedings of SPIE, page 1513-1520. SPIE, (2003)Fast block-matching algorithm using selective integral projections.J. Lee, and J. Ra. VCIP, volume 4671 of Proceedings of SPIE, page 454-463. SPIE, (2002)A fast multi-resolution block matching algorithm and its LSI architecture for low bit-rate video coding.J. Lee, K. Lim, B. Song, and J. Ra. IEEE Trans. Circuits Syst. Video Techn., 11 (12): 1289-1301 (2001)Block motion estimation based on selective integral projections.J. Lee, and J. Ra. ICIP (1), page 689-692. IEEE, (2002)13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.I. Choi, S. Hong, K. Kim, J. Hwang, S. Woo, Y. Kim, C. Cho, E. Lee, H. Lee, M. Jung and 27 other author(s). ISSCC, page 234-236. IEEE, (2024)User-Directed Privacy Protection in the Ubiquitous Environment.J. Lee, J. Park, and S. Kim. EUC (2), page 37-42. IEEE Computer Society, (2008)978-0-7695-3492-3.Regression Tree CNN for Estimation of Ground Sampling Distance Based on Floating-Point Representation.J. Lee, and S. Sull. Remote Sensing, 11 (19): 2276 (2019)Variable block size motion estimation algorithm and its hardware architecture for H.264/AVC.J. Lee, and N. Lee. ISCAS (3), page 741-744. IEEE, (2004)Dual-Mode RFID Tag IC Supporting Gen-2 and Visible RFID Modes Using a Process-Compensating Self-Calibrating Clock Generator.A. ud Din, J. Lee, N. Hieu, and J. Lee. IEEE Trans. Ind. Electron., 67 (1): 569-580 (2020)A New VLSI Architecture of a Hierarchical Motion Estimator for Low Bit-Rate Video Coding.J. Lee, S. Kim, S. Jang, and J. Ra. ICIP (2), page 774-778. IEEE, (1999)

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Disambiguation of "Lee, Hun-Jae"

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13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.

Please choose a person to relate this publication to

Jae-Hun Kim

Jae-Hun Jeoung

Kang-Hun Lee

Hun Dae Lee

Seung-Hun Lee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lee, Hun-Jae"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.

Please choose a person to relate this publication to

Jae-Hun Kim

Jae-Hun Jeoung

Kang-Hun Lee

Hun Dae Lee

Seung-Hun Lee

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.