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13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.

I. Choi, S. Hong, K. Kim, J. Hwang, S. Woo, Y. Kim, C. Cho, E. Lee, H. Lee, M. Jung, H. Jung, J. Hwang, J. Yoon, W. Lim, H. Yoo, W. Lee, J. Oh, D. Lee, J. Lee, J. Kim, Y. Kim, S. Park, B. Ho, B. Na, H. Choi, C. Lee, S. Lee, H. Shin, Y. Lee, J. Ryu, S. Shin, S. Park, D. Lim, S. Bae, Y. Sohn, T. Oh, и S. Hwang. ISSCC, стр. 234-236. IEEE, (2024)

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Jae-Hun Kim

Jae-Hun Jeoung

Kang-Hun Lee

Hun Dae Lee

Seung-Hun Lee

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Dual-Mode RFID Tag IC Supporting Gen-2 and Visible RFID Modes Using a Process-Compensating Self-Calibrating Clock Generator.A. ud Din, J. Lee, N. Hieu, и J. Lee. IEEE Trans. Ind. Electron., 67 (1): 569-580 (2020)Variable block size motion estimation algorithm and its hardware architecture for H.264/AVC.J. Lee, и N. Lee. ISCAS (3), стр. 741-744. IEEE, (2004)Regression Tree CNN for Estimation of Ground Sampling Distance Based on Floating-Point Representation.J. Lee, и S. Sull. Remote Sensing, 11 (19): 2276 (2019)Fast block-matching algorithm using selective integral projections.J. Lee, и J. Ra. VCIP, том 4671 из Proceedings of SPIE, стр. 454-463. SPIE, (2002)Fast half-pixel motion estimation based on a directional search and a linear model.Y. Lee, J. Lee, и J. Ra. VCIP, том 5150 из Proceedings of SPIE, стр. 1513-1520. SPIE, (2003)A fast multi-resolution block matching algorithm and its LSI architecture for low bit-rate video coding.J. Lee, K. Lim, B. Song, и J. Ra. IEEE Trans. Circuits Syst. Video Techn., 11 (12): 1289-1301 (2001)Block motion estimation based on selective integral projections.J. Lee, и J. Ra. ICIP (1), стр. 689-692. IEEE, (2002)13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.I. Choi, S. Hong, K. Kim, J. Hwang, S. Woo, Y. Kim, C. Cho, E. Lee, H. Lee, M. Jung и 27 other автор(ы). ISSCC, стр. 234-236. IEEE, (2024)User-Directed Privacy Protection in the Ubiquitous Environment.J. Lee, J. Park, и S. Kim. EUC (2), стр. 37-42. IEEE Computer Society, (2008)978-0-7695-3492-3.VLSI architecture design of motion vector processor for H.264/AVC.K. Yoo, J. Lee, и K. Sohn. ICIP, стр. 1412-1415. IEEE, (2008)