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Efficient test-point selection for scan-based BIST.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (4): 667-676 (1998)

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Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch., , , , and . ASP-DAC/VLSI Design, page 598-603. IEEE Computer Society, (2002)The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data., , , , , and . ITC, page 998-1007. IEEE Computer Society, (2003)Enhanced Controllability for IDDQ Test Sets Using Partial Scan., , , and . DAC, page 278-281. ACM, (1991)Integration of partial scan and built-in self-test., , and . J. Electron. Test., 7 (1-2): 125-137 (1995)DFTEXPERT: An Expert System for Design of Testable VLSI Circuits., and . IEA/AIE (Vol. 1), page 388-396. ACM, (1988)Core Based ASIC Design., and . VLSI Design, page 10. IEEE Computer Society, (2000)An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch., , , and . J. Electron. Test., 18 (4-5): 475-485 (2002)Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme., , and . DAC, page 748-753. ACM Press, (1999)A Hybrid Algorithm for Test Point Selection for Scan-Based BIST., , , and . DAC, page 478-483. ACM Press, (1997)Efficient test-point selection for scan-based BIST., , , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (4): 667-676 (1998)