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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.

B. Zimmer, R. Venkatesan, Y. Shao, J. Clemons, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. Tell, Y. Zhang, W. Dally, J. Emer, C. Gray, S. Keckler, and B. Khailany. IEEE J. Solid State Circuits, 55 (4): 920-932 (2020)

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Hua Shao

Li Shao

Hua Shao

Junyang Shao

Yaping Shao

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Timeloop: A Systematic Approach to DNN Accelerator Evaluation.A. Parashar, P. Raina, Y. Shao, Y. Chen, V. Ying, A. Mukkara, R. Venkatesan, B. Khailany, S. Keckler, and J. Emer. ISPASS, page 304-315. IEEE, (2019)Full Stack Optimization of Transformer Inference: a Survey.S. Kim, C. Hooper, T. Wattanawong, M. Kang, R. Yan, H. Genc, G. Dinh, Q. Huang, K. Keutzer, M. Mahoney and 2 other author(s). CoRR, (2023)Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis.R. Garibotti, B. Reagen, Y. Shao, G. Wei, and D. Brooks. IEEE Trans. Circuits Syst. II Express Briefs, 65-II (10): 1440-1444 (2018)DiffuseLoco: Real-Time Legged Locomotion Control with Diffusion from Offline Datasets.X. Huang, Y. Chi, R. Wang, Z. Li, X. Peng, Y. Shao, B. Nikolic, and K. Sreenath. CoRR, (2024)DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators.C. Hong, Q. Huang, G. Dinh, M. Subedar, and Y. Shao. MICRO, page 209-224. ACM, (2023)NeuroVectorizer: End-to-End Vectorization with Deep Reinforcement Learning.A. Haj-Ali, N. Ahmed, T. Willke, Y. Shao, K. Asanovic, and I. Stoica. CoRR, (2019)Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.A. Amid, D. Biancolin, A. Gonzalez, D. Grubb, S. Karandikar, H. Liew, A. Magyar, H. Mao, A. Ou, N. Pemberton and 7 other author(s). IEEE Micro, 40 (4): 10-21 (2020)Code Transpilation for Hardware Accelerators.Y. Nishida, S. Bhatia, S. Laddad, H. Genc, Y. Shao, and A. Cheung. CoRR, (2023)Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design.Q. Huang, C. Hong, J. Wawrzynek, M. Subedar, and Y. Shao. ISPASS, page 277-287. IEEE, (2022)Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration.H. Genc, S. Kim, A. Amid, A. Haj-Ali, V. Iyer, P. Prakash, J. Zhao, D. Grubb, H. Liew, H. Mao and 9 other author(s). DAC, page 769-774. IEEE, (2021)

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Disambiguation of "Shao, Yakun Sophia"

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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.

Please choose a person to relate this publication to

Hua Shao

Li Shao

Hua Shao

Junyang Shao

Yaping Shao

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shao, Yakun Sophia"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.

Please choose a person to relate this publication to

Hua Shao

Li Shao

Hua Shao

Junyang Shao

Yaping Shao

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.