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From RTL Liveness Assertions to Cost-Effective Hardware Checkers., , , и . DCIS, стр. 1-6. IEEE, (2018)Automated Design Error Localization in RTL Designs., , , , , , , , и . IEEE Des. Test, 31 (1): 83-92 (2014)Fully-Fusible Convolutional Neural Networks for End-to-End Fused Architecture with FPGA Implementation., , , , и . ICECS, стр. 1-5. IEEE, (2023)Enhancing Fault Resilience of QNNs by Selective Neuron Splitting., , , , и . AICAS, стр. 1-5. IEEE, (2023)Mutation analysis for SystemC designs at TLM., , , , , , , и . LATW, стр. 1-6. IEEE, (2011)High-Level Decision Diagrams based coverage metrics for verification and test., , , , и . LATW, стр. 1-6. IEEE, (2009)An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics., , , и . ITC-Asia, стр. 61-66. IEEE, (2018)Layout to Logic Defect Analysis for Hierarchical Test Generation., , , , и . DDECS, стр. 35-40. IEEE Computer Society, (2007)Low-area boundary BIST architecture for mesh-like network-on-chip., и . DDECS, стр. 95-100. IEEE, (2012)Extensible open-source framework for translating RTL VHDL IP cores to SystemC., , и . DDECS, стр. 112-115. IEEE Computer Society, (2013)