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Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , и 3 other автор(ы). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)A Holistic Solution for Reliability of 3D Parallel Systems., , , , и . ACM J. Emerg. Technol. Comput. Syst., 18 (1): 23:1-23:27 (2022)xURLCC in 6g with meshed RAN., , , , , и . CoRR, (2023)HE-PEx: Efficient Machine Learning under Homomorphic Encryption using Pruning, Permutation and Expansion., , , , , , , , , и 1 other автор(ы). CoRR, (2022)SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator., , , , , и . MICRO, стр. 1005-1021. ACM, (2021)A New Design of an N-Bit Reversible Arithmetic Logic Unit., , , , и . ISED, стр. 224-225. IEEE Computer Society, (2014)HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework., , , , , , , и . IISWC, стр. 13-24. IEEE, (2020)Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective., , , и . ISPASS, стр. 202-211. IEEE, (2019)Towards Closing the Programmability-Efficiency Gap using Software-Defined Hardware.. University of Michigan, USA, (2021)Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators., , , и . ISPASS, стр. 240-242. IEEE, (2021)