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Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes.

K. Zhou, Channakeshav, M. Chu, J. Guo, S. Liu, R. Kraft, C. You, and J. McDonald. FPT, page 182-188. IEEE, (2002)

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Zhou Zhou

Pei Kuang

Zhou Zhou

Kuan Tong

Kuan Yang

Other publications of authors with the same name

On-chip dynamic programming networks using 3D-TSV integration.R. Al-Dujaily, T. Mak, K. Zhou, K. Lam, Y. Meng, A. Yakovlev, and C. Poon. ICSAMOS, page 318-325. IEEE, (2011)Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory.C. You, J. Guo, R. Kraft, M. Chu, R. Heikaus, O. Erdogan, P. Curran, B. Goda, K. Zhou, and J. McDonald. FPL, volume 2778 of Lecture Notes in Computer Science, page 11-20. Springer, (2003)3D direct vertical interconnect microprocessors test vehicle.J. Mayega, O. Erdogan, P. Belemjian, K. Zhou, J. McDonald, and R. Kraft. ACM Great Lakes Symposium on VLSI, page 141-146. ACM, (2003)A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology.J. Guo, C. You, K. Zhou, B. Goda, R. Kraft, and J. McDonald. FPGA, page 145-153. ACM, (2003)The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA.J. Guo, C. You, P. Curran, M. Chu, K. Zhou, J. Diao, A. George, R. Kraft, and J. McDonald. ACM Great Lakes Symposium on VLSI, page 141-144. ACM, (2004)A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.K. Zhou, M. Chu, C. You, J. Guo, Channakeshav, J. Mayega, J. McDonald, R. Kraft, and B. Goda. FPGA, page 248. ACM, (2003)Triple-rail MOS current mode logic for high-speed self-timed pipeline applications.K. Zhou, Y. Luo, S. Chen, A. Drake, J. McDonald, and T. Zhang. ISCAS, IEEE, (2006)Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes.K. Zhou, Channakeshav, M. Chu, J. Guo, S. Liu, R. Kraft, C. You, and J. McDonald. FPT, page 182-188. IEEE, (2002)The gigahertz FPGA: design consideration and applications.J. Guo, C. You, M. Chu, R. Heikaus, K. Zhou, O. Erdogan, J. Diao, B. Goda, R. Kraft, and J. McDonald. FPGA, page 248. ACM, (2004)Dynamic Block Size Adjustment and Workload Balancing Strategy Based on CPU-GPU Heterogeneous Platform.J. Fang, K. Zhou, C. Tan, and H. Zhao. ISPA/BDCloud/SocialCom/SustainCom, page 999-1006. IEEE, (2019)

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Disambiguation of "Zhou, Kuan"

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Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes.

Please choose a person to relate this publication to

Zhou Zhou

Pei Kuang

Zhou Zhou

Kuan Tong

Kuan Yang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zhou, Kuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes.

Please choose a person to relate this publication to

Zhou Zhou

Pei Kuang

Zhou Zhou

Kuan Tong

Kuan Yang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes.