( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA.

, , , , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 141-144. ACM, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Zhou Zhou

Pei Kuang

Zhou Zhou

Kuan Tong

Kuan Yang

 

Другие публикации лиц с тем же именем

On-chip dynamic programming networks using 3D-TSV integration., , , , , , и . ICSAMOS, стр. 318-325. IEEE, (2011)A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology., , , , , и . FPGA, стр. 145-153. ACM, (2003)3D direct vertical interconnect microprocessors test vehicle., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 141-146. ACM, (2003)Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory., , , , , , , , , и . FPL, том 2778 из Lecture Notes in Computer Science, стр. 11-20. Springer, (2003)The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA., , , , , , , , и . ACM Great Lakes Symposium on VLSI, стр. 141-144. ACM, (2004)A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme., , , , , , , , и . FPGA, стр. 248. ACM, (2003)Triple-rail MOS current mode logic for high-speed self-timed pipeline applications., , , , , и . ISCAS, IEEE, (2006)Dynamic Block Size Adjustment and Workload Balancing Strategy Based on CPU-GPU Heterogeneous Platform., , , и . ISPA/BDCloud/SocialCom/SustainCom, стр. 999-1006. IEEE, (2019)Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes., , , , , , , и . FPT, стр. 182-188. IEEE, (2002)Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques., , , , , , и . FPL, том 2438 из Lecture Notes in Computer Science, стр. 414-423. Springer, (2002)