Author of the publication

Revealing Ordered Polymer Packing during Freeze-Drying Fabrication of a Bulk Heterojunction Poly(3-hexylthiophene-2,5-diyl):6,6-Phenyl-C61-butyric Acid Methyl Ester Layer: In Situ Optical Spectroscopy, Molecular Dynamics Simulation, and X-ray Diffraction

, , , , , , , , and . The Journal of Physical Chemistry C, 121 (27): 14826--14834 (June 2017)
DOI: 10.1021/acs.jpcc.7b01679

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches., , , , , , and . ISLPED, page 1-6. IEEE, (2017)Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications., , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (2): 247-257 (2016)A low store energy and robust ReRAM-based flip-flop for normally off microprocessors., , , , , , , , and . ISCAS, page 2803-2806. IEEE, (2016)An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology., , , , , , , , , and 5 other author(s). VLSI Technology and Circuits, page 262-263. IEEE, (2022)An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 59 (7): 2297-2309 (July 2024)A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 290-291. IEEE, (2022)A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture., , , , , , and . APCCAS, page 461-464. IEEE, (2016)Revealing Ordered Polymer Packing during Freeze-Drying Fabrication of a Bulk Heterojunction Poly(3-hexylthiophene-2,5-diyl):6,6-Phenyl-C61-butyric Acid Methyl Ester Layer: In Situ Optical Spectroscopy, Molecular Dynamics Simulation, and X-ray Diffraction, , , , , , , , and . The Journal of Physical Chemistry C, 121 (27): 14826--14834 (June 2017)