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Disambiguation of "Kaul, Himanshu"

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250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS.

, , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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Himanshu Raj

Himanshu Verma

Himanshu Tyagi

Himanshu Ghildiyal

Himanshu Patel

 

Other publications of authors with the same name

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , and . ESSCIRC, page 210-213. IEEE, (2010)Near-threshold voltage (NTV) design: opportunities and challenges., , , , , and . DAC, page 1153-1158. ACM, (2012)A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS., , , , , , , and . VLSIC, page 118-119. IEEE, (2012)A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS., , , , , , , , , and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS., , , , , , and . ESSCIRC, page 177-180. IEEE, (2012)High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS.. SoCC, page 324. IEEE, (2005)Active shielding of RLC global interconnects., , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 98-104. ACM, (2002)DVS for On-Chip Bus Designs Based on Timing Error Correction., , , , and . DATE, page 80-85. IEEE Computer Society, (2005)A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS., , , , , , , and . ISSCC, page 182-184. IEEE, (2012)