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Disambiguation of "Saito, Yoshiki"

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Power reduction techniques for Dynamically Reconfigurable Processor Arrays.

, , , , , , , and . FPL, page 305-310. IEEE, (2008)

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Yoshiki Hayashi

Kaku Saito

Itohei Saito

Yoshiki Terazono

Yoshiki Mori

 

Other publications of authors with the same name

Geyser-2: The second prototype CPU with fine-grained run-time power gating., , , , , , , , , and 7 other author(s). ASP-DAC, page 87-88. IEEE, (2011)Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping., , , , , , , and . FPT, page 349-352. IEEE, (2010)Cache Controller Design on Ultra Low Leakage Embedded Processors., , , , , , and . ARCS, volume 5455 of Lecture Notes in Computer Science, page 171-182. Springer, (2009)Cool Mega-Array: A highly energy efficient reconfigurable accelerator., , , , , , , , , and . FPT, page 1-8. IEEE, (2011)Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique., , , , , , , , , and 1 other author(s). FPT, page 329-332. IEEE, (2008)An early Holocene sea-level jump and delta initiation, and . Geophysical Research Letters, 34 (18): L18401+ (Sep 18, 2007)Power reduction techniques for Dynamically Reconfigurable Processor Arrays., , , , , , , and . FPL, page 305-310. IEEE, (2008)Area change detection in river mouthbars at the Mekong River delta using Synthetic Aperture Radar (SAR) data., , , and . IGARSS, page 4911-4914. IEEE, (2012)MuCCRA-3: a low power dynamically reconfigurable processor array., , , , , , and . ASP-DAC, page 377-378. IEEE, (2010)Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells., , , and . FPT, page 104-111. IEEE Computer Society, (2009)