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Disambiguation of "Ha, Yajun"

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Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation.

, , , , , , , and . DAC, page 613-618. IEEE, (2021)

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Yajun Fang

Yajun Xiao

Yajun Cheng

Hoang Ha

Ngo Ha

 

Other publications of authors with the same name

Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects., , , , and . PDPTA, CSREA Press, (2000)Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications., , , , , , , , , and 2 other author(s). CoRR, (2023)HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (11): 4295-4308 (November 2023)An energy-efficient system on a programmable chip platform for cloud applications., , , , , , and . J. Syst. Archit., (2017)Unified data authenticated encryption for vehicular communication., , and . MWSCAS, page 1-4. IEEE, (2016)Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)., and . FPGA, page 268. ACM, (2012)Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2156-2169 (2019)An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model., and . ASP-DAC, page 886-891. IEEE, (2006)Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools., , , and . FPL, page 279-284. IEEE, (2007)ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning., , and . FPL, page 1-11. IEEE, (2016)