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Disambiguation of "Fayazi, Morteza"

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A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.

, , , , , , , , , , , and . VLSI Technology and Circuits, page 202-203. IEEE, (2022)

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Morteza Rad

Morteza Aleyassin

Morteza Scharifzadeh

Morteza Charifi

Morteza Ghaseminia

 

Other publications of authors with the same name

Open Information Extraction: A Review of Baseline Techniques, Approaches, and Applications., , , , and . CoRR, (2023)A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET., , , , , , , , , and 2 other author(s). VLSI Technology and Circuits, page 202-203. IEEE, (2022)A Simplified Approach to Two-Port Analysis in Feedback., , and . CoRR, (2019)Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)An Open-source Framework for Autonomous SoC Design with Analog Block Generation., , , , , , , , , and 3 other author(s). VLSI-SOC, page 141-146. IEEE, (2020)Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation., , , , , , , , , and 5 other author(s). VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 65-85. Springer, (2020)FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method., , , , and . ICCAD, page 1-8. IEEE, (2023)Tablext: A combined neural network and heuristic based table extractor., , , , , and . Array, (2022)Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm., , , , , , , , , and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging., , , , , and . CICC, page 1-2. IEEE, (2023)