Author of the publication

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.

, , , , , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Holistic Solution for Reliability of 3D Parallel Systems., , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (1): 23:1-23:27 (2022)xURLCC in 6g with meshed RAN., , , , , and . CoRR, (2023)Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator., , , , , and . MICRO, page 1005-1021. ACM, (2021)HE-PEx: Efficient Machine Learning under Homomorphic Encryption using Pruning, Permutation and Expansion., , , , , , , , , and 1 other author(s). CoRR, (2022)A New Design of an N-Bit Reversible Arithmetic Logic Unit., , , , and . ISED, page 224-225. IEEE Computer Society, (2014)HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework., , , , , , , and . IISWC, page 13-24. IEEE, (2020)Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective., , , and . ISPASS, page 202-211. IEEE, (2019)Towards Closing the Programmability-Efficiency Gap using Software-Defined Hardware.. University of Michigan, USA, (2021)Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators., , , and . ISPASS, page 240-242. IEEE, (2021)