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Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture.

, , , and . NOCS, page 139-148. IEEE Computer Society, (2008)

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An Introduction to Multi-Core System on Chip - Trends and Challenges., , , , , and . Multiprocessor System-on-Chip, Springer, (2011)Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET., , , , and . ISCAS, page 2127-2130. IEEE, (2013)Network-on-chip traffic modeling for data flow applications., and . RAPIDO, page 2:1-2:6. ACM, (2013)Convergence analysis of run-time distributed optimization on adaptive systems using game theory., , , , and . FPL, page 555-558. IEEE, (2008)Power consumption analysis and energy efficient optimization for turbo decoder implementation., , , , and . SoC, page 12-17. IEEE, (2010)A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits., , , , , , and . ICICDT, page 81-84. IEEE, (2013)Using OxRRAM memories for improving communications of reconfigurable FPGA architectures., , , , , , and . NANOARCH, page 65-69. IEEE Computer Society, (2011)Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory., , , , and . ISVLSI, page 422-427. IEEE Computer Society, (2010)Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC., , , and . NOCS, page 129-138. IEEE Computer Society, (2008)Reconfigurable nanoscale logic cells : a comparison study., , , and . ICECS, page 483-486. IEEE, (2009)