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Test set selection for structural faults in analog IC's., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (7): 1026-1039 (1999)Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (6): 288-298 (2003)A BIST Design of Structured Arrays with Fault-Tolerant Layout., and . ITC, page 514-521. IEEE Computer Society, (1988)Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter., , , and . CICC, page 161-164. IEEE, (2007)Mixed-signal on-chip timing measurements.. Integr., 26 (1-2): 151-165 (1998)An equivalent-time and clocked approach for continuous-time quantization., , , , , , , and . ISCAS, page 2529-2532. IEEE, (2011)Data jitter measurement using a delta-time-to-voltage converter method., , , and . ITC, page 1-7. IEEE Computer Society, (2007)Analog fault models: Back to the future?. ITC, page 1. IEEE Computer Society, (2014)Testing clock distribution circuits using an analytic signal method., , , , , and . ITC, page 323-331. IEEE Computer Society, (2001)Analytical fault modeling and static test generation for analog ICs., and . ICCAD, page 44-47. IEEE Computer Society / ACM, (1994)