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Disambiguation of "Yamaguchi, Takahiro J."

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Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (6): 288-298 (2003)

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Shigeo Yamaguchi

Takahiro Kato

Takahiro Moriyama

Fabian Yamaguchi

Ichiro Yamaguchi

 

Other publications of authors with the same name

Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology., , , , and . ICECS, page 220-223. IEEE, (2011)A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer., , , and . ISCAS, page 93-96. IEEE, (2014)Post-Silicon Jitter Measurements., , , and . Asian Test Symposium, page 258-263. IEEE Computer Society, (2012)A New Procedure for Measuring High-Accuracy Probability Density Functions., , , , , , and . Asian Test Symposium, page 185-190. IEEE Computer Society, (2012)A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals., , , , , and . VTS, page 102-110. IEEE Computer Society, (2001)A clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . VLSIC, page 142-143. IEEE, (2012)Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . ASP-DAC, page 103-104. IEEE, (2013)Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements., , , , and . ITC, page 58-66. IEEE Computer Society, (2003)A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems., , , , , , and . ITC, page 77-84. IEEE Computer Society, (2004)A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter., , , , and . ITC, page 717-725. IEEE Computer Society, (2002)