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Disambiguation of "Saxena, Nirmal R."

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Refined Bounds on Signature Analysis Aliasing for Random Testing.

, , and . ITC, page 818-827. IEEE Computer Society, (1991)

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Abhinav Saxena

Ambrish Saxena

Sabine Saxena

Amit Saxena

Krishna Saxena

 

Other publications of authors with the same name

On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors., , , , and . ITC, page 1-10. IEEE, (2020)Error Model (EM) - A New Way of Doing Fault Simulation., and . ITC, page 324-333. IEEE, (2022)Characterizing and Mitigating Soft Errors in GPU DRAM., , , , , , , , and . MICRO, page 641-653. ACM, (2021)Finite state machine synthesis with concurrent error detection., , and . ITC, page 672-679. IEEE Computer Society, (1999)How Many Test Patterns are Useless?, , , and . VTS, page 23-28. IEEE Computer Society, (2008)Low Overhead Tag Error Mitigation for GPU Architectures., , , , and . DSN, page 314-321. IEEE Computer Society, (2018)Design Verification of a Super-Scalar RISC Processor., , , , , , , and . FTCS, page 472-477. IEEE Computer Society, (1995)Techniques for Estimation of Design Diversity for Combinational Logic Circuits., , and . DSN, page 25-36. IEEE Computer Society, (2001)Optimizing Large-Scale Fault Injection Experiments through Martingale Hypothesis: A Systematic Approach for Reliability Assessment of Safety-Critical Systems., , , , and . DSN-S, page 111-117. IEEE, (2024)Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks., and . IEEE Trans. Computers, 39 (7): 969-975 (1990)