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Disambiguation of "Tripathi, Jai Narayan"

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Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator.

, , , , , and . ISCAS, page 1-5. IEEE, (2019)

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Aditya Narayan Tripathi

Jai Ben Prasad Tripathi

Pratibha Tripathi

Chandrabhal Tripathi

Jai Prakash

 

Other publications of authors with the same name

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations., , , , , and . Sensors, 21 (18): 6074 (2021)Blood Pressure Estimation from ECG Data Using XGBoost and ANN for Wearable Devices., , , and . ICECS 2022, page 1-4. IEEE, (2022)A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell., , , and . ISCAS, page 1-5. IEEE, (2023)Designing Asymmetric 2.4 GHz RF Oscillator for improving Signal Integrity by Design of Experiments., , and . APCCAS, page 640-643. IEEE, (2010)Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization., , , , and . ISQED, page 525-528. IEEE, (2012)Decoupling network optimization in high speed systems by mixed-integer programming., , , , , and . ISCAS, page 1010-1013. IEEE, (2014)Fast Analysis of Time Interval Error in Current-Mode Drivers., , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (2): 367-377 (2018)Nonlinear modeling and analysis of buck converter using volterra series., , , and . ICECS, page 222-226. IEEE, (2017)I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)., , , and . VLSI-SoC, page 226-227. IEEE, (2019)Cost-effective optimization of serial link system for Signal Integrity and Power Integrity., , and . ISQED, page 548-552. IEEE, (2011)