( en | de | ru )

 

Disambiguation of "Gupta, Navneet"

Author of the publication

copydeleteadd this publication to your clipboard
Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator.

, , , , , and . ISCAS, page 1-5. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Navneet Dalal

Navneet Kumar

Ashutosh Kumar Gupta

Renee Gupta

Ajay Kumar Gupta

 

Other publications of authors with the same name

16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell., , , , and . ESSDERC, page 356-359. IEEE, (2016)A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS., , and . ISCAS, page 1-5. IEEE, (2019)1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell., , , , and . ESSCIRC, page 316-319. IEEE, (2017)Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes., , , , and . IWASI, page 266-270. IEEE, (2015)TFET NDR skewed inverter based sensing method., , , , , and . NANOARCH, page 13-14. ACM, (2016)Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator., , , , , and . ISCAS, page 1-5. IEEE, (2019)Energy efficiency optimization for digital applications in 28nm UTBB FDSOI technology., , , , and . MIXDES, page 23. IEEE, (2015)A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan., , , , , , , , , and 1 other author(s). COOL CHIPS, page 1-3. IEEE, (2020)3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications., , , , and . DATE, page 361-366. IEEE, (2016)Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications., , , , and . ISQED, page 107-112. IEEE, (2016)