( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
SHARC: A streaming model for FPGA accelerators and its application to Saliency.

, , и . DATE, стр. 1237-1242. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

 

Другие публикации лиц с тем же именем

Influence of compiler optimizations on system power., , , и . DAC, стр. 304-307. ACM, (2000)Hardware and Software Techniques for Controlling DRAM Power Modes., , , , и . IEEE Trans. Computers, 50 (11): 1154-1173 (2001)Modeling steep slope devices: From circuits to architectures., , , , , , и . DATE, стр. 1-6. European Design and Automation Association, (2014)Design space exploration of workload-specific last-level caches., , , , и . ISLPED, стр. 243-248. ACM, (2012)Design and analysis of an NoC architecture from performance, reliability and energy perspective., , , , и . ANCS, стр. 173-182. ACM, (2005)A low latency router supporting adaptivity for on-chip interconnects., , , , и . DAC, стр. 559-564. ACM, (2005)Ferroelectric Transistor based Non-Volatile Flip-Flop., , , , , и . ISLPED, стр. 10-15. ACM, (2016)A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays., , , , , и . ASP-DAC, стр. 118-123. IEEE, (2015)Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)., , , , и . FPGA, стр. 265. ACM, (2005)Editorial., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (1): 1 (2015)