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Power Estimation of Embedded Multiplier Blocks in FPGAs.

, and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 835-839 (2010)

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Power Estimation of Embedded Multiplier Blocks in FPGAs., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 835-839 (2010)Architectural synthesis of DSP circuits under simultaneous error and time constraints., and . VLSI-SoC, page 322-327. IEEE, (2010)Precision-wise architectural synthesis of DSP circuits., and . EUSIPCO, page 562-566. IEEE, (2010)Adding Value to TCP/IP Based Information exchange Security by Specialized Hardware., , and . SECURWARE, page 145-150. IEEE Computer Society, (2007)Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources., , , and . SoC, page 1-4. IEEE, (2006)Floorplan-based FPGA interconnect power estimation in DSP circuits., , and . SLIP, page 53-60. ACM, (2009)A Generator of High-Speed Floating-Point Modules., , , and . FCCM, page 306-307. IEEE Computer Society, (2004)A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components., , and . ReConFig, page 361-366. IEEE Computer Society, (2008)SQNR estimation of non-linear fixed-point algorithms., , , and . EUSIPCO, page 522-526. IEEE, (2010)Analysis of limit cycles by means of affine arithmetic computer-aided tests., , , and . EUSIPCO, page 991-994. IEEE, (2004)