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A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.

M. Li, G. Huang, X. Wu, L. Qian, X. Zeng, and D. Zhou. Sci. China Inf. Sci., 59 (8): 082401:1-082401:16 (2016)

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Jinglan Wu

Recovery of citric acid from fermentation broth using simulated moving bed technology: = Reinigung von Zitronensäure aus Fermentationslösung durch kontinuierliche ChromatographieJ. Wu. Uni Erlangen-Nürnberg, (2009)

Jinjin Wu

Haiyan Wu

Changzhu Wu

Yinghua Wu

Other publications of authors with the same name

Radiation-hardened 14T SRAM cell by polar design for space applications.L. Hao, B. Qiang, C. Dai, C. Peng, W. Lu, Z. Lin, L. Liu, Q. Zhao, X. Wu, and F. Sun. IEICE Electron. Express, 20 (13): 20230083 (2023)A Timing-Shared Adaptive Sensing Methodology for Low-Voltage SRAM.Y. Zhou, Z. Yang, Y. Wei, X. Lin, S. Wu, W. Lu, C. Peng, X. Li, and X. Wu. ISCAS, page 1-5. IEEE, (2024)SRAM-Based Digital CIM Macro for Linear Interpolation and MAC.Z. Lin, Y. Liu, Y. Wang, Y. Zhao, C. Peng, and X. Wu. ISCAS, page 1-5. IEEE, (2024)Design of radiation-hardened memory cell by polar design for space applications.L. Hao, L. Liu, Q. Shi, B. Qiang, Z. Li, N. Liu, C. Dai, Q. Zhao, C. Peng, W. Lu and 2 other author(s). Microelectron. J., (February 2023)Flip Point Offset-Compensation Sense Amplifier With Sensing-Margin-Enhancement for Dynamic Random-Access Memory.L. Liu, D. Tai, B. Qiang, L. Guan, C. Peng, C. Dai, L. Hao, W. Lu, Z. Lin, Q. Zhao and 1 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 1759-1763 (April 2024)First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology.K. Wang, Y. Wu, Y. Ren, R. Wei, Z. Chen, J. Hang, Z. Wang, F. Zhang, L. Zhang, C. Peng and 8 other author(s). ESSDERC, page 13-16. IEEE, (2023)Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design.L. Hao, Y. Wang, Y. Liu, S. Zhao, X. Zhang, Y. Li, W. Lu, C. Peng, Q. Zhao, Y. Zhou and 3 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 32 (5): 883-896 (May 2024)A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design.S. Gao, J. Chen, D. Ke, and X. Wu. APCCAS, page 1465-1468. IEEE, (2006)14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.Z. Yuan, Y. Yang, J. Yue, R. Liu, X. Feng, Z. Lin, X. Wu, X. Li, H. Yang, and Y. Liu. ISSCC, page 232-234. IEEE, (2020)A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.Z. Lin, S. Zhang, Q. Jin, J. Xia, Y. Liu, K. Yu, J. Zheng, X. Xu, X. Fan, K. Li and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 31 (6): 776-788 (June 2023)

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Disambiguation of "Wu, Xiulong"

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A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.

Please choose a person to relate this publication to

Jinglan Wu

Jinjin Wu

Haiyan Wu

Changzhu Wu

Yinghua Wu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wu, Xiulong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.

Please choose a person to relate this publication to

Jinglan Wu

Jinjin Wu

Haiyan Wu

Changzhu Wu

Yinghua Wu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
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A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.