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Disambiguation of "Kim, Yong-Bin"

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A 10-bit 64MS/s SAR ADC using variable clock period method.

, , and . MWSCAS, page 1144-1147. IEEE, (2013)

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Yong Bin Sun

Se Bin Kim

Ok Bin Kim

Sang-Bin Kim

Yong-Ho Kim

 

Other publications of authors with the same name

Variable bit truncation technique for approximate stochastic computing (ASC)., , , , and . ISOCC, page 73-74. IEEE, (2017)A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction., and . ISCAS, page 1-4. IEEE, (2017)A novel 32-bit scalable multiplier architecture., , and . ACM Great Lakes Symposium on VLSI, page 241-244. ACM, (2003)An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction., , , , and . NATW, page 6-11. IEEE, (2016)A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers., , , , , and . MWSCAS, page 599-602. IEEE, (2014)Full custom implementation of a S-Box circuit architecture using power gated PLA structure., , and . MWSCAS, page 294-297. IEEE, (2014)Design flow of robust routed power distribution for low power ASIC., and . ISCAS (1), page 181-184. IEEE, (2002)A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC., and . ACM Great Lakes Symposium on VLSI, page 215-219. ACM, (2016)SET-based nano-circuit simulation and design method using HSPICE., , and . ACM Great Lakes Symposium on VLSI, page 344-347. ACM, (2004)Gate Diffusion Input Multi-Threshold Null Convention Logic Circuit Design Approach., , , and . ISOCC, page 282-283. IEEE, (2020)