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Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach.

, , , , , , , , , , , , , , and . SAMOS, volume 11733 of Lecture Notes in Computer Science, page 416-428. Springer, (2019)

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Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms., , , , and . SiPS, page 127-129. IEEE, (2016)CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF., , , , , , , , , and 11 other author(s). CF, page 320-325. ACM, (2019)Run-time performance monitoring of hardware accelerators: POSTER., and . CF, page 289-291. ACM, (2019)Verification of Neural Networks: Challenges and Perspectives in the AIDOaRt Project (Short Paper)., , , , , and . IPS/RiCeRcA/SPIRIT@AI*IA, volume 3345 of CEUR Workshop Proceedings, CEUR-WS.org, (2022)Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems., and . ReConFig, page 1-4. IEEE, (2016)NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology., , , , , , and . CF, page 183-189. ACM, (2019)Power and clock gating modelling in coarse grained reconfigurable systems., , , , and . Conf. Computing Frontiers, page 384-391. ACM, (2016)Power modelling for saving strategies in coarse grained reconfigurable systems., , , , and . ReConFig, page 1-4. IEEE, (2015)Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures., , , , and . J. Electr. Comput. Eng., (2016)An integrated hardware/software design methodology for signal processing systems., , , , , , , , , and 1 other author(s). J. Syst. Archit., (2019)