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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

B. Çatli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. Ahmadi, H. Maarefi, A. Momtaz, and N. Kocaman. CICC, page 1-4. IEEE, (2013)

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Momtaz Sedrak

Afshin Bassiri

Afshin Sepehri

Afshin Abbasi

Other publications of authors with the same name

3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS.A. Nazemi, K. Hu, B. Çatli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, and J. Cao. ISSCC, page 1-3. IEEE, (2015)A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.B. Zhang, A. Nazemi, A. Garg, N. Kocaman, M. Ahmadi, M. Khanpour, H. Zhang, J. Cao, and A. Momtaz. ISSCC, page 34-35. IEEE, (2013)A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS.A. Garg, U. Singh, N. Huang, W. Wong, B. Liu, Z. Huang, A. Momtaz, and J. Cao. VLSIC, page 1-2. IEEE, (2014)Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS.G. Li, W. Lee, D. Cui, B. Zhang, A. Momtaz, and J. Cao. A-SSCC, page 1-4. IEEE, (2015)A fully integrated SONET OC-48 transceiver in standard CMOS.A. Momtaz, J. Cao, M. Caresosa, A. Hairapetian, D. Chung, K. Vakilian, M. Green, W. Tan, K. Jen, I. Fujimori and 1 other author(s). IEEE J. Solid State Circuits, 36 (12): 1964-1973 (2001)2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.U. Singh, A. Garg, B. Raghavan, N. Huang, H. Zhang, Z. Huang, A. Momtaz, and J. Cao. ISSCC, page 40-41. IEEE, (2014)18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.G. Li, A. Garg, T. He, U. Singh, J. Zhang, L. Rao, C. Liu, M. Nazari, Y. Liu, Y. Liu and 9 other author(s). ISSCC, page 338-340. IEEE, (2024)A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.B. Raghavan, D. Cui, U. Singh, H. Maarefi, D. Pi, A. Vasani, Z. Huang, A. Momtaz, and J. Cao. ISSCC, page 32-33. IEEE, (2013)A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.B. Çatli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. Ahmadi, H. Maarefi, A. Momtaz and 1 other author(s). CICC, page 1-4. IEEE, (2013)An 8.5-11.5Gbps SONET transceiver with referenceless frequency acquisition.N. Kocaman, S. Fallahi, M. Kargar, M. Khanpour, and A. Momtaz. CICC, page 1-4. IEEE, (2012)

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Disambiguation of "Momtaz, Afshin"

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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

Please choose a person to relate this publication to

Momtaz Sedrak

Momtaz Sedrak

Afshin Bassiri

Afshin Sepehri

Afshin Abbasi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Momtaz, Afshin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

Please choose a person to relate this publication to

Momtaz Sedrak

Momtaz Sedrak

Afshin Bassiri

Afshin Sepehri

Afshin Abbasi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.