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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.

B. Çatli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. Ahmadi, H. Maarefi, A. Momtaz, и N. Kocaman. CICC, стр. 1-4. IEEE, (2013)

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Momtaz Sedrak

Afshin Bassiri

Afshin Sepehri

Afshin Abbasi

Другие публикации лиц с тем же именем

A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.B. Zhang, A. Nazemi, A. Garg, N. Kocaman, M. Ahmadi, M. Khanpour, H. Zhang, J. Cao, и A. Momtaz. ISSCC, стр. 34-35. IEEE, (2013)3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS.A. Nazemi, K. Hu, B. Çatli, D. Cui, U. Singh, T. He, Z. Huang, B. Zhang, A. Momtaz, и J. Cao. ISSCC, стр. 1-3. IEEE, (2015)A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS.A. Garg, U. Singh, N. Huang, W. Wong, B. Liu, Z. Huang, A. Momtaz, и J. Cao. VLSIC, стр. 1-2. IEEE, (2014)Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS.G. Li, W. Lee, D. Cui, B. Zhang, A. Momtaz, и J. Cao. A-SSCC, стр. 1-4. IEEE, (2015)2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.U. Singh, A. Garg, B. Raghavan, N. Huang, H. Zhang, Z. Huang, A. Momtaz, и J. Cao. ISSCC, стр. 40-41. IEEE, (2014)A fully integrated SONET OC-48 transceiver in standard CMOS.A. Momtaz, J. Cao, M. Caresosa, A. Hairapetian, D. Chung, K. Vakilian, M. Green, W. Tan, K. Jen, I. Fujimori и 1 other автор(ы). IEEE J. Solid State Circuits, 36 (12): 1964-1973 (2001)18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.G. Li, A. Garg, T. He, U. Singh, J. Zhang, L. Rao, C. Liu, M. Nazari, Y. Liu, Y. Liu и 9 other автор(ы). ISSCC, стр. 338-340. IEEE, (2024)A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.B. Raghavan, D. Cui, U. Singh, H. Maarefi, D. Pi, A. Vasani, Z. Huang, A. Momtaz, и J. Cao. ISSCC, стр. 32-33. IEEE, (2013)A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications.B. Çatli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. Ahmadi, H. Maarefi, A. Momtaz и 1 other автор(ы). CICC, стр. 1-4. IEEE, (2013)Digital wireline and PLL techniques.G. Wei, и A. Momtaz. CICC, IEEE, (2009)

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Momtaz Sedrak

Momtaz Sedrak

Afshin Bassiri

Afshin Sepehri

Afshin Abbasi

Другие публикации лиц с тем же именем

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