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Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids.

, and . ICECS, page 658-661. IEEE, (2008)

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Density-reduction-oriented layer assignment for rectangle escape routing., , and . ACM Great Lakes Symposium on VLSI, page 275-278. ACM, (2012)Timing-constrained replacement using spare cells for design changes., and . ACM Great Lakes Symposium on VLSI, page 347-348. ACM, (2013)IO connection assignment and RDL routing for flip-chip designs., and . ASP-DAC, page 588-593. IEEE, (2009)Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids., and . ICECS, page 658-661. IEEE, (2008)Flexible escape routing for flip-chip designs., and . ICECS, page 352-355. IEEE, (2008)Utilization of multi-bit flip-flops for clock power reduction., and . ICECS, page 677-680. IEEE, (2012)Timing-constrained I/O buffer placement for flip-chip designs., and . DATE, page 619-624. IEEE, (2011)Continuous K-Nearest Neighbor Query over Moving Objects in Road Networks., , and . APWeb/WAIM, volume 5446 of Lecture Notes in Computer Science, page 27-38. Springer, (2009)Two-sided single-detour untangling for bus routing., and . DAC, page 206-211. ACM, (2010)Top-down-based symmetrical buffered clock routing., , and . ACM Great Lakes Symposium on VLSI, page 75-78. ACM, (2012)