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A Background Calibration Technique to Control the Bandwidth of Digital PLLs.

, , , , , and . IEEE J. Solid State Circuits, 53 (11): 3243-3255 (2018)

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An efficient method to compute phase-noise in injection-locked frequency dividers., , , and . ISCAS, page 1753-1756. IEEE, (2013)Background adaptive linearization of high-speed digital-to-analog Converters., , , and . ISCAS, page 582-585. IEEE, (2013)Bang-bang digital PLLs.. ESSCIRC, page 329-334. IEEE, (2016)Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter., , , , and . CICC, page 133-136. IEEE, (2006)Fast-switching analog PLL with finite-impulse response., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (9): 1697-1701 (2004)A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , and . IEEE J. Solid State Circuits, 58 (9): 2466-2477 (September 2023)Phase noise in digital frequency dividers., , , , and . IEEE J. Solid State Circuits, 39 (5): 775-784 (2004)Phase Noise Analysis of Periodically ON/OFF Switched Oscillators., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (1): 54-63 (January 2023)Fast-switching analog PLL with finite-impulse response., , , and . ISCAS (4), page 165-168. IEEE, (2004)Phase noise and accuracy in quadrature oscillators., , , , and . ISCAS (1), page 161-164. IEEE, (2004)