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Disambiguation of "Lacaita, Andrea L."

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Phase noise in digital frequency dividers.

, , , , and . IEEE J. Solid State Circuits, 39 (5): 775-784 (2004)

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Other publications of authors with the same name

A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs., , , and . MIPRO, page 74-79. IEEE, (2014)Differential tuning oscillators with reduced flicker noise upconversion., , , , and . ICECS, page 33-36. IEEE, (2004)A multi-tank LC-oscillator microwave oscillator example., , , , and . ICECS, page 29-32. IEEE, (2004)Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology., , , , and . IEEE J. Solid State Circuits, 57 (6): 1788-1799 (2022)A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop., , , and . IEEE J. Solid State Circuits, 36 (4): 611-619 (2001)A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (3): 481-488 (2006)A Background Calibration Technique to Control the Bandwidth of Digital PLLs., , , , , and . IEEE J. Solid State Circuits, 53 (11): 3243-3255 (2018)A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration., , , and . IEEE J. Solid State Circuits, 48 (10): 2419-2429 (2013)Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band., , , , and . IEEE J. Solid State Circuits, 48 (10): 2375-2389 (2013)A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop., , , , , and . IEEE J. Solid State Circuits, 50 (11): 2678-2691 (2015)