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Disambiguation of "Chen, Mike Shuo-Wei"

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A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency.

, and . ISSCC, page 74-76. IEEE, (2019)

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Wei Chen

Wei Chen

Wei Chen

Wei Chen

Wei Chen

 

Other publications of authors with the same name

A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS., and . ISSCC, page 394-396. IEEE, (2018)Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications., , , , , and . ICC, page 5769-5774. IEEE, (2007)16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS., and . ISSCC, page 262-264. IEEE, (2020)High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range., and . CICC, page 1-8. IEEE, (2022)27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS., and . ISSCC, page 456-457. IEEE, (2016)A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS., , and . CICC, page 1-4. IEEE, (2013)Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling., , , , and . ICCAD, page 119:1-119:9. IEEE, (2020)Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms., , , , , and . ASP-DAC, page 100-107. IEEE, (2022)A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems., , , , , , , , , and 4 other author(s). CICC, page 1-2. IEEE, (2023)A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter., , and . IEEE J. Solid State Circuits, 52 (9): 2335-2349 (2017)