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A genetic algorithm framework for test generation.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 1034-1044 (1997)

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A genetic algorithm framework for test generation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 1034-1044 (1997)K2: an estimator for peak sustainable power of VLSI circuits., , and . ISLPED, page 178-183. ACM, (1997)A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults., and . VLSI Design, page 498-505. IEEE Computer Society, (1999)Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation., , and . IOLTW, page 65-. IEEE Computer Society, (2001)Diagnostic Fault Simulation of Sequential Circuits., , and . ITC, page 178-186. IEEE Computer Society, (1992)Enhancing high-level control-flow for improved testability., , and . ICCAD, page 322-328. IEEE Computer Society / ACM, (1996)Use of a field programmable gate array for education in manufacturing test and automatic test equipment., , and . IEEE Trans. Educ., 44 (3): 239-245 (2001)Diagnostic test generation for sequential circuits., , and . ITC, page 225-234. IEEE Computer Society, (2000)At-speed logic BIST using a frozen clock testing strategy., , , and . ITC, page 64-71. IEEE Computer Society, (2001)Partial Scan Selection Based on Dynamic Reachability and Observability Information., , , and . VLSI Design, page 174-180. IEEE Computer Society, (1998)