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Disambiguation of "Ge, Fen"

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Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (10): 3041-3054 (2016)

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Fen Wang

Fen Guo

Fen Zhou

Junbo Ge

Wancheng Ge

 

Other publications of authors with the same name

Design and Implementation of LSTM Accelerator Based on FPGA., , , , , and . ICCT, page 1675-1679. IEEE, (2020)Hardware Trojan Detection Method for Gate-Level Netlists Based on the Idea of Few-Shot Learning., , , , and . ICCT, page 301-305. IEEE, (2021)Reconfigurable Multi-algorithm Neural Network Accelerator Based on Target Detection., , , and . ICCT, page 1555-1559. IEEE, (2022)A Hybrid CNN Compression Approach for Hardware Acceleration., , , , and . ICCT, page 1546-1550. IEEE, (2022)An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units., , , and . ICCT, page 1521-1525. IEEE, (2022)A two-phase floorplanning approach for Application-specific Network-on-Chip., , , and . ASICON, page 1-4. IEEE, (2013)Exploring memory controller configurations for many-core systems with 3D stacked DRAMs., , , and . ISQED, page 565-570. IEEE, (2015)A network components insertion method for 3D application-specific Network-on-Chip., , , and . ASICON, page 1-4. IEEE, (2015)Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (10): 3041-3054 (2016)A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture., , and . ASICON, page 1-5. IEEE, (2023)