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Reconfiguration in FPGA-based multi-core platforms for hard real-time applications.

, , and . ReCoSoC, page 1-8. IEEE, (2016)

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Future directions in clocking multi-ghz systems., and . ISLPED, page 219. ACM, (2002)A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 301-310. Springer, (2004)Towards a tailored mixed-precision sub-8-bit quantization scheme for Gated Recurrent Units using Genetic Algorithms., , , , , and . CoRR, (2024)Reconfiguration in FPGA-based multi-core platforms for hard real-time applications., , and . ReCoSoC, page 1-8. IEEE, (2016)A Time-predictable TTEthenet Node., , , and . ISORC, page 229-233. IEEE, (2019)Design of delay insensitive circuits using multi-ring structures., , and . EURO-DAC, page 15-20. IEEE Computer Society Press, (1992)S4NOC: a minimalistic network-on-chip for real-time multicores., , and . NoCArc@MICRO, page 8:1-8:6. ACM, (2019)A Neural Network Engine for Resource Constrained Embedded Systems., , , , and . ACSSC, page 125-131. IEEE, (2020)A Network Traffic Generator Model for Fast Network-on-Chip Simulation., , , , , and . DATE, page 780-785. IEEE Computer Society, (2005)A light-weight statically scheduled network-on-chip., , and . NORCHIP, page 1-6. IEEE, (2012)