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Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned.

M. Radulovic, K. Asifuzzaman, D. Zivanovic, N. Rajovic, G. de Verdière, D. Pleiter, M. Marazakis, N. Kallimanis, P. Carpenter, P. Radojkovic, and E. Ayguadé. SBAC-PAD, page 250-257. IEEE, (2018)

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Peter Radojkovic

Petar Kolev

Petar Stoilov

Petar Gregus

Petar Smetiško

Other publications of authors with the same name

Towards resilient EU HPC systems: a blueprint.P. Radojkovic. CF, page 339. ACM, (2019)DRAM Errors and Cosmic Rays: Space Invaders or Science Fiction?I. Boixaderas, J. Amaya, S. Moré, J. Bartolome, D. Vicente, O. Unsal, D. Gizopoulos, P. Carpenter, P. Radojkovic, and E. Ayguadé. SBAC-PAD, page 194-205. IEEE, (2024)Large-Memory Nodes for Energy Efficient High-Performance Computing.D. Zivanovic, M. Radulovic, G. Llort, D. Zaragoza, J. Strassburg, P. Carpenter, P. Radojkovic, and E. Ayguadé. MEMSYS, page 3-9. ACM, (2016)Enabling a reliable STT-MRAM main memory simulation.K. Asifuzzaman, R. Verdejo, and P. Radojkovic. MEMSYS, page 283-292. ACM, (2017)Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?M. Radulovic, D. Zivanovic, D. Ruiz, B. de Supinski, S. McKee, P. Radojkovic, and E. Ayguadé. MEMSYS, page 31-36. ACM, (2015)Cost-aware prediction of uncorrected DRAM errors in the field.I. Boixaderas, D. Zivanovic, S. Moré, J. Bartolome, D. Vicente, M. Casas, P. Carpenter, P. Radojkovic, and E. Ayguadé. SC, page 61. IEEE/ACM, (2020)Characterizing the resource-sharing levels in the UltraSPARC T2 processor.V. Cakarevic, P. Radojkovic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero. MICRO, page 481-492. ACM, (2009)Energy Efficient HPC on Embedded SoCs: Optimization Techniques for Mali GPU.I. Grasso, P. Radojkovic, N. Rajovic, I. Gelado, and A. Ramírez. IPDPS, page 123-132. IEEE Computer Society, (2014)Main memory latency simulation: the missing link.R. Verdejo, K. Asifuzzaman, M. Radulovic, P. Radojkovic, E. Ayguadé, and B. Jacob. MEMSYS, page 107-116. ACM, (2018)Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors.P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero. IEEE Trans. Parallel Distributed Syst., 24 (12): 2513-2525 (2013)

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Disambiguation of "Radojkovic, Petar"

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Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned.

Please choose a person to relate this publication to

Peter Radojkovic

Petar Kolev

Petar Stoilov

Petar Gregus

Petar Smetiško

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Radojkovic, Petar"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned.

Please choose a person to relate this publication to

Peter Radojkovic

Petar Kolev

Petar Stoilov

Petar Gregus

Petar Smetiško

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned.