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Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning.

Y. Wang, Y. Qin, D. Deng, J. Wei, T. Chen, X. Lin, L. Liu, S. Wei, и S. Yin. IEEE J. Solid State Circuits, 57 (10): 3164-3178 (2022)

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Lin Lin

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Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures.X. Lin, S. Yin, L. Liu, и S. Wei. ASP-DAC, стр. 456-461. IEEE, (2016)LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA.X. Lin, S. Yin, F. Tu, L. Liu, X. Li, и S. Wei. DAC, стр. 16:1-16:6. ACM, (2018)Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning.Y. Wang, Y. Qin, D. Deng, J. Wei, T. Chen, X. Lin, L. Liu, S. Wei, и S. Yin. IEEE J. Solid State Circuits, 57 (10): 3164-3178 (2022)A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation.Y. Wang, Y. Qin, D. Deng, J. Wei, T. Chen, X. Lin, L. Liu, S. Wei, и S. Yin. VLSI Circuits, стр. 1-2. IEEE, (2021)Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only).S. Yin, D. Liu, L. Sun, X. Lin, L. Liu, и S. Wei. FPGA, стр. 295. ACM, (2017)Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips.S. Wei, X. Lin, F. Tu, Y. Wang, L. Liu, и S. Yin. IEEE Trans. Circuits Syst. I Regul. Pap., 70 (3): 1228-1241 (марта 2023)Wafer-scale Computing: Advancements, Challenges, and Future Perspectives.Y. Hu, X. Lin, H. Wang, Z. He, X. Yu, J. Zhang, Q. Yang, Z. Xu, S. Guan, J. Fang и 5 other автор(ы). CoRR, (2023)ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training.X. Lin, L. Sun, F. Tu, L. Liu, X. Li, S. Wei, и S. Yin. DAC, стр. 751-756. IEEE, (2021)

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