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Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell., , , , , and . ESSCIRC, page 211-214. IEEE, (2004)A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor., , , , , , , , , and 2 other author(s). ISSCC, page 2564-2571. IEEE, (2006)7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor., , , , , , , , and . ISSCC, page 324-325. IEEE, (2013)Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor., , , , , , , , , and 2 other author(s). ICCD, page 258-263. IEEE Computer Society, (1998)High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor., , , and . ICCD, page 247-252. IEEE Computer Society, (1997)Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 49 (1): 9-18 (2014)4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor., , , , , , , , and . ISSCC, page 1728-1734. IEEE, (2006)Design SRAMs for burn-in., , , , and . VTS, page 164-170. IEEE Computer Society, (1993)4.1 22nm Next-generation IBM System z microprocessor., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2015)Design of the Power6 Microprocessor., , , , , , , , , and 7 other author(s). ISSCC, page 96-97. IEEE, (2007)