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Disambiguation of "Sayyaparaju, Sagarvarma"

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A Scan Register Based Access Scheme for Multilevel Non-Volatile Memristor Memory.

, , , , and . ICECS, page 630-633. IEEE, (2019)

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Other publications of authors with the same name

A Mixed-Mode Neuron with On-chip Tunability for Generic Use in Memristive Neuromorphic Systems., , and . ISVLSI, page 441-446. IEEE Computer Society, (2018)Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems., , , and . ACM Great Lakes Symposium on VLSI, page 479-482. ACM, (2017)Fabrication and Performance of Hybrid ReRAM-CMOS Circuit Elements for Dynamic Neural Networks., , , , , , , , and . ICONS, page 6:1-6:4. ACM, (2019)A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems., , , , , and . SoCC, page 37-42. IEEE, (2018)Circuit Techniques for Efficient Implementation of Memristor Based Reservoir Computing., , , and . ISCAS, page 1-5. IEEE, (2020)A mixed-signal approach to memristive neuromorphic system design., , , and . MWSCAS, page 547-550. IEEE, (2017)A practical hafnium-oxide memristor model suitable for circuit design and simulation., , , , and . ISCAS, page 1-4. IEEE, (2017)A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systems., , and . ISQED, page 69-74. IEEE, (2018)Device-aware Circuit Design for Robust Memristive Neuromorphic Systems with STDP-based Learning., , , and . ACM J. Emerg. Technol. Comput. Syst., 16 (3): 28:1-28:25 (2020)A Scan Register Based Access Scheme for Multilevel Non-Volatile Memristor Memory., , , , and . ICECS, page 630-633. IEEE, (2019)