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A Scan Register Based Access Scheme for Multilevel Non-Volatile Memristor Memory.

, , , , and . ICECS, page 630-633. IEEE, (2019)

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A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems., , , , , and . SoCC, page 37-42. IEEE, (2018)Circuit Techniques for Efficient Implementation of Memristor Based Reservoir Computing., , , and . ISCAS, page 1-5. IEEE, (2020)On-Chip Interface for Event based Sensor and Spiking Neuromorphic Processing., , , and . MWSCAS, page 1-4. IEEE, (2022)A Novel Scan-In Scheme for CMOS/ReRAM Programmable Logic Circuits., , and . ISCAS, page 1-5. IEEE, (2018)Stochasticity in Neuromorphic Computing: Evaluating Randomness for Improved Performance., , , , and . ICECS, page 454-457. IEEE, (2019)Evaluating online-learning in memristive neuromorphic circuits., , , , , , and . NCS, page 5:1-5:8. ACM, (2017)Capacitor-Less Memristive Integrate-and-Fire Neuron with Stochastic Behavior., , , and . MWSCAS, page 175-178. IEEE, (2021)Design Considerations for Insulator Metal Transition based Artificial Neurons., , , and . MWSCAS, page 1131-1134. IEEE, (2019)Device-aware Circuit Design for Robust Memristive Neuromorphic Systems with STDP-based Learning., , , and . ACM J. Emerg. Technol. Comput. Syst., 16 (3): 28:1-28:25 (2020)A Scan Register Based Access Scheme for Multilevel Non-Volatile Memristor Memory., , , , and . ICECS, page 630-633. IEEE, (2019)