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A Task-Centric Memory Model for Scalable Accelerator Architectures.

, , , , и . IEEE Micro, 30 (1): 29-39 (2010)

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Другие публикации лиц с тем же именем

A Hybrid Shared Memory/Message Passing Parallel Machine., и . ICPP (1), стр. 232-236. CRC Press, (1993)SPARTAN: A software tool for Parallelization Bottleneck Analysis., и . IWMSE@ICSE, стр. 56-63. IEEE Computer Society, (2009)A Task-Centric Memory Model for Scalable Accelerator Architectures., , , , и . PACT, стр. 77-87. IEEE Computer Society, (2009)SUDS: automatic parallelization for raw processors.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2003)ndltd.org (oai:dspace.mit.edu:1721.1/17591).LoGPC: Modeling Network Contention in Message-Passing Programs., и . IEEE Trans. Parallel Distributed Syst., 12 (4): 404-415 (2001)A Task-Centric Memory Model for Scalable Accelerator Architectures., , , , и . IEEE Micro, 30 (1): 29-39 (2010)Fetch-Criticality Reduction through Control Independence., , , и . ISCA, стр. 13-24. IEEE Computer Society, (2008)Emµcode: Masking hard faults in complex functional units., , и . DSN, стр. 458-467. IEEE Computer Society, (2009)FlexCache: A Framework for Flexible Compiler Generated Data Caching., , и . Intelligent Memory Systems, том 2107 из Lecture Notes in Computer Science, стр. 135-146. Springer, (2000)Implications of I/O for Gang Scheduled Workloads., , , , и . JSSPP, том 1291 из Lecture Notes in Computer Science, стр. 215-237. Springer, (1997)